Analog Intern

2027 Summer Intern PHD or Master with self-driven research capability is preferred. (Must not have graduated before September 2027)

May 24 - August 13

San Jose, CA - 100% onsite

Renesas MID (Memory Interface Division) is looking for an Analog intern to help the group on the development of the next generation DDR PMIC.

During the time of the intern, they will focus on the research of a PMIC control architecture which could be the solution of our next generation DDR PMIC. They will get support from DE and AE, do simulation on different level and build circuit in Cadence.

It is a unique opportunity for young talent to build industry skillset and develop their own career version.

Good performance during the intern time will lead to an offer of full-time job at Renesas.

Requirements

PHD or Master with self-driven research capability is preferred. (Must not have graduated before September 2027); The candidate should have solid background on Power Electronics and Analog design.; They should be familiar with behavior simulation tool like SIMPLIS and transistor level design environment in Cadence.