Analog Layout Engineer _RBCN/ME

Location: Shanghai

Job Description
1. Independently complete the layout design and verification of analog circuits based on circuit schematics and design specifications.

2. Collaborate closely with circuit designers to optimize layout designs and meet circuit performance requirements (matching, noise, power consumption, etc.).

3. Ensure completed layouts comply with company internal layout guideline and pass sign-off criteria.

4. Resolve technical issues arising during layout design to ensure compliance with requirements and keep project timelines.

Qualifications
- Master or bachelor's degree in microelectronics or other related subjects

- >= 2ys experience in IC analog layout

- Finish module-level analog layout independently

- Understand top level floor plan and adjust module level layouts to fit the top layout

- Good understanding of semiconductor process(CMOS is a must , BCD is preferred) and common devices

- Familiar with parasitic effects, matching techniques, and antenna effects involved in layout design processes.

- Basic Usage of Linux/Unix

- Familiar with Cadence/Mentor based tools

- Flexibility and good capacity for communication and teamwork

- English is a must- Have interesting in tools or process, willing to learn further, and take on corresponding work.

Responsibilities

Independently complete the layout design and verification of analog circuits based on circuit schematics and design specifications.; Collaborate closely with circuit designers to optimize layout designs and meet circuit performance requirements (matching, noise, power consumption, etc.).; Ensure completed layouts comply with company internal layout guideline and pass sign-off criteria.; Resolve technical issues arising during layout design to ensure compliance with requirements and keep project timelines.

Requirements

Master or bachelor's degree in microelectronics or other related subjects; >= 2ys experience in IC analog layout; Finish module-level analog layout independently; Understand top level floor plan and adjust module level layouts to fit the top layout; Good understanding of semiconductor process(CMOS is a must , BCD is preferred) and common devices; Familiar with parasitic effects, matching techniques, and antenna effects involved in layout design processes.; Basic Usage of Linux/Unix; Familiar with Cadence/Mentor based tools; Flexibility and good capacity for communication and teamwork; English is a must- Have interesting in tools or process, willing to learn further, and take on corresponding work.