Design Verification Engineer - SoC

We are seeking a Design Verification Engineer to join our Systems/Performance Verification team. You will ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.

Responsibilities

Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon); Work closely with software and application developers on identifying performance bottlenecks and tuning the software; Develop test plans and test infrastructure/tools for performance tuning, correlation, and verification; Improve and maintain the architectural performance models; Develop tests in SystemVerilog, Python, or vectors to debug and correlate the RTL and performance model; Develop SystemVerilog or Python-based checkers for verifying the performance features; Develop coverage monitors and analyze coverage to ensure all performance features are covered; Debug performance issues and conduct performance tuning on silicon; Drive end-to-end performance tuning, ensuring optimal hardware utilization, software efficiency, and architectural alignment across the ASIC design lifecycle.

Requirements

Strong understanding of digital design, RTL, and ASIC design flows; Hands-on experience with performance verification, simulation, and modeling; Comfortable developing checkers, coverage monitors, and testbenches in SystemVerilog; Skilled in writing Python scripts for automation, data analysis, and performance modeling; Experience building and maintaining performance models for chip subsystems; Understanding of memory hierarchies, pipelines, interconnects, and compute accelerators; Familiarity with performance bottleneck analysis, compiler optimizations, and workload tuning; Some exposure to kernel level performance metrics and profiling tools.

Benefits

Medical, dental, and vision packages with generous premium coverage; $500 per month credit for waiving medical benefits; Various wellness benefits covering fitness, mental health, and more; Daily lunch + dinner in our office; Unlimited compute budget subject to ROI justification.