Experienced PCIe System Design Engineer

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.

Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.

Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.

We are looking for a hands-on System Engineer, focused on the design, implementation, and silicon validation of PCIe interfaces within our SoC. The role requires a deep understanding of protocol layers, detailed design of the controller and its integration, and performing deep-level hardware debugging and silicon bring-up to ensure high-speed connectivity and NVMe compatibility.

Responsibilities

PCIe Design & Configuration: Defining and implementing PCIe Controller and PHY IP; Protocol Logic Implementation: Implementing PCIe-specific features such as DOE, IDE, MFND/SR-IOV; IP Integration & CSRs: Integrating PCIe/PHY IPs into the SoC fabric and defining/implementing the Control and Status Registers (CSRs) for hardware-firmware interaction; Power & Reset Design: Designing power management mechanisms (ASPM, L1 Substates) and system-level reset sequences; Silicon Bring-up: Performing PCIe link bring-up on silicon, testing connectivity, and optimizing the data path; Advanced Debug: Troubleshooting multi-discipline complex issues using advanced AI debug tools and traditional equipment such protocol analyzers and oscilloscopes

Requirements

7+ years of experience as a System/Design/Validation Engineer with a strong focus on PCIe; Deep expertise in PCIe Gen 4/5 standards (Gen 6 is a major plus); Technical knowledge of NVMe protocol (Queue management, Admin/IO commands); Hands-on experience with PCIe protocol analyzers and high-speed oscilloscopes; Proficient in Python/C for test automation and hardware debugging; B.Sc. in Electrical Engineering or Computer Engineering from a leading academic institution; Ability to work in a multidisciplinary configuration and collaborate with diverse teams