Principal Engineer, ASIC Development Engineering (Mixed Signal IP Layout)

We are looking for technically sound and highly skilled Analog/High Speed DDR IO Layout designer with 8-12 years of experience. The ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems.

Responsibilities

Develop and optimize MSIP IC layouts in TSMC 3nm, ensuring high performance and manufacturability; Collaborate with design engineers to understand design requirements and translate them into precise layouts; Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently; Work closely with the physical design team to integrate custom blocks into the overall chip design; Identify and resolve layout-related issues, providing creative solutions to meet design specifications; Conduct design reviews and provide technical feedback to improve layout practices and methodologies; Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes

Requirements

8-12 years of experience in Analog/High Speed DDR IO IC layout design; Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics; Hands-on experience with custom layout design for Analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, High speed DDR IOs; Familiarity with custom digital layout (i.e. high speed logic paths); Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding); Strong understanding of analog/IO design principles, including circuit performance and parasitic effects; Aware of layout techniques to mitigate ESD, latch-up issues; Advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 5nm and below; Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating; Experience with layout optimization for power, performance, and area (PPA) metrics; Excellent problem-solving skills and attention to detail; Effective communication and teamwork abilities; Bachelor’s or Master’s degree in Electronics or Electrical Engineering

Nice to have

Any prior AI knowledge/experience which can improve Layout development effort and QoR is a big plus; Knowledge of scripting languages (e.g., Skill, TCL and SVRF) for automation tasks