Principal Engineer- Custom Layout (High-Speed Interface IP)

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

Job Summary

We are seeking an experienced Principal Custom Layout Engineer to lead the physical implementation of advanced high-speed analog and mixed-signal circuits for next-generation interface IPs. The successful candidate will be responsible for the layout design, floorplanning, optimization, and signoff of critical analog and mixed-signal blocks including DFE, CTLE, PLLs, CDRs, Transmitters, Receivers, DLLs, and SerDes subsystems.

The ideal candidate will have 15+ years of custom layout experience after completing a Master’s or Bachelor’s degree from a reputed university, with a proven record of delivering silicon-proven designs in advanced process nodes such as 5nm and 3nm. The candidate should be able to independently drive complex projects and mentor a team of 3–4 junior layout engineers.

Responsibilities

Lead the custom layout development of high-performance analog and mixed-signal IPs for advanced semiconductor products.; Independently drive complex custom layout projects from floorplanning through tapeout.; Own physical implementation for critical building blocks such as rCTLE, DFE, PLL, etc.; Define floorplanning strategies to achieve aggressive performance, area, power, and yield targets.; Perform transistor-level and device matching-aware layouts using industry best practices.; Drive physical verification and signoff activities, including DRC, LVS, ERC, PERC, density verification, and EMIR analysis.; Work closely with Analog Design, Digital Design, SI, Packaging, and Product Engineering teams to ensure successful product execution.; Support silicon bring-up, debug, characterization, and production qualification activities.; Develop and institutionalize layout methodologies and best practices across the organization.

Requirements

B.Tech/M.Tech in Electrical Engineering, Electronics Engineering, VLSI Design, or related discipline from a reputed university.; 15+ years of industry experience in custom layout design.; Extensive experience in custom layout of analog and mixed-signal circuits in advanced CMOS technologies.; Strong understanding of:; Analog layout fundamentals; Device matching techniques; High-speed signal routing; Noise coupling mechanisms; Parasitic extraction and optimization; Manufacturing process variations; Demonstrated track record of delivering successful silicon in advanced technology nodes.