Principal Engineer , DFT

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

Renesas is seeking a highly experienced Principal DFT Engineer to drive end-to-end DFT execution for advanced SoCs/MCUs. The candidate should possess deep expertise across the complete DFT lifecycle, from test architecture definition through silicon bring-up and production test deployment.

Proven expertise in

- DFT Architecture & Test Planning
- DFT RTL Design & Integration
- Scan Insertion & ATPG
- MBIST, LBIST, JTAG/IJTAG
- GLS & Signoff
- Silicon Bring-up, Debug & Diagnosis
- Strong hands-on experience with Tessent, Genus/Fusion Compiler, VCS/Xcelium, and Conformal/Formality.
- Strong automation and scripting skills using Python, TCL, Perl, or Shell.
- Leadership & Soft Skills
- Strong technical leadership with the ability to influence cross-functional and global teams.
- Demonstrated ownership, accountability, and execution excellence.
- Excellent analytical, problem-solving, and debugging skills.
- Proven mentoring and coaching capabilities to develop engineering talent.
- Self-motivated, collaborative, and results-oriented with a continuous improvement mindset.

Responsibilities

Define and drive SoC-level DFT architecture and test strategy, including Scan, ATPG, MBIST, LBIST, JTAG/IJTAG, SSN, and test compression.; Own the complete DFT flow from test architecture, RTL design & integration, DFT verification, scan insertion, ATPG, coverage closure, and signoff.; Drive silicon bring-up, silicon debug, diagnosis, yield improvement, and production test enablement.; Develop and deploy scalable DFT methodologies, automation frameworks, and best practices.; Collaborate with Design, Verification, Physical Design, and Test Engineering teams.; Provide technical leadership and mentor engineers across projects.

Requirements

B.E./B.Tech., M.E./M.Tech., or Ph.D. in Electronics or related field.; 15+ years of hands-on DFT experience with successful delivery of multiple SoCs.