Senior Engineer -Performance Verification

We specialize in the top-level verification of cutting-edge ASICs that power complex high-performance systems. Our designs are either monolithic ASICs or integrated multi-chip-modules holding several hundreds of processor cores, DSPs as well as ARM cores, tailored hardware accelerator IPs and many high-speed interfaces, including Ethernet, CPRI, and PCIe. As a Performance Verification Engineer, you'll be part of a team tackling some of the most challenging verification tasks in the industry, ensuring that our ASICs meet our high standards for performance, functionality, and security. You will play an important role in the team developing environments and/or tests run in SystemC/TLM simulation, RTL environments, hardware emulation, and eventually on Silicon.

Responsibilities

Perform RTL performance analysis, analyze throughput, latency, bandwidth, QoS, cache efficiency and memory utilization; Implement performance verification plans at SoC-level and performance debug using both simulation and emulation environments; Collaborate with architecture, design, software and verification teams to define performance requirements and ensure alignment with overall system goals; Analyze and optimize system performance, including DDR, CPU, Interconnects and high-speed interfaces like PCIe, UCIe etc; Understanding of cache coherency, memory hierarchy, DDR, NoC, and interconnect architectures; Experience with high-speed protocols such as PCIe, Ethernet, AXI or DDR; Experience with performance simulation tools; Leverage AI-based tools and automation to improve engineering productivity and performance analysis workflows; Participate in defining/documenting verification strategies for the parts of the ASIC assigned to you as a verifier; Debug RTL designs/Testcases with help of EDA simulation tools, HW emulator and SW debuggers; Contribute to keeping tests clean in the CI regression running on all platforms; Develop tests involving UVM VIPs; Do formal connectivity verification and gate level simulation (GLS); Compile the ASIC designs to run in HW emulators, like Siemens Veloce and Cadence Palladium; Script and develop and maintain the TLV CI flow in projects, including visualization of results

Requirements

Solid C programming skills targeting ASICs or other type of embedded software programming; Solid skills in RTL debugging issues in simulations of SystemVerilog or VHDL designs; Using SW debuggers, waveforms windows etc. for HW/SW co-debugging of C-code running in the ASIC; GLS; Coresight and other JTAG TAP related features; Compiling designs for HW emulation; Formal connectivity verification; High speed interfaces like Ethernet, PCIe, CPRI; ARM CPUs/cores, SMMU; AMBA interconnect, preferably using Cadence STG or IWB

Nice to have

Desired knowledge and experience in using SW debuggers for HW/SW co-debugging; Experience of multi core designs is a plus; Debugging tests running on HW Emulators and or Silicon; Simulating and debugging tests running on SystemC/TLM platforms; Power aware verification (digital, not mixed signal); Using Formal tools for power verification; Lab experience suitable for bring-up of ASIC Silicon prototypes; XPROP; GLS with timing, Power aware GLS