Senior Package Design Engineer

Renesas is a global semiconductor company providing hardware and software solutions for a range of cutting-edge technologies including self-driving cars, robots, automated factory equipment, and smart home applications. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas is a global, multi-billion dollar, publicly traded company headquartered in Japan, and has subsidiaries in 20 countries worldwide. Renesas is a dynamic, multi-cultural technology company where employees learn, mentor, innovate and thrive. Renesas is extending our share in fast-growing data economy-related markets such as infrastructure and data center and strengthening our presence in the industrial/IOT and automotive segments. Our solutions drive products developed by major innovators around the world. Join us and build your future by being part of what’s next in electronics.

We are looking for a Package Design Engineer to join our advanced silicon packaging design and simulation team and contribute to the design and delivery of high‑performance 2.5D/3D, chiplet‑based, FCBGA, SiP, wire bond and QFP/QFN packages used in industry‑leading products. The role requires strong technical depth in package layout execution, manufacturability, and cross‑domain co‑design with silicon, SI/PI, thermal, and reliability teams.

Responsibilities

Perform package layout design and development for advanced packages including 2.5D/3D IC, FCBGA, SiP, and multi‑chip modules.; Develop and maintain package CAD databases, ensuring accuracy and adherence to design guidelines, Design for Manufacturing (DFM), and Design for Assembly (DFA) requirements to ensure producibility.; Manage end-to-end design cycle, including schematic creation, netlist import, footprint assignment, and generation of manufacturing outputs (Gerbers, drill data, fabrication/assembly drawings).; Create and modify substrate/RDL layouts, bump maps, escape routing, and power/ground structures.; Work closely with SI/PI, thermal, reliability, and DFT teams to support co‑design and optimization and participate in design reviews.; Ensure designs comply with foundry, OSAT, and manufacturing design rules (DRC, LVS).; Support ECO cycles, design updates, and version control throughout the project lifecycle.

Requirements

6+ years of hands‑on experience in package CAD layout and development.; Strong experience with 2.5D / 3D IC packaging, FCBGA and advanced substrate‑based packages, multi‑die and chiplet‑based designs.; Proficiency in industry‑standard tools such as: Cadence Allegro Package Designer (APD / SiP), Siemens Xpedition / Innovator 3D IC, or equivalent.; Experience working with advanced manufacturing design rules and interface with OSATs.; Good understanding of Signal Integrity (SI) and Power Integrity (PI) fundamentals and High‑Speed Design concepts.; Strong communication, presentation, and documentation skills with the ability to work effectively in a team environment.