Silicon Test Engineer – ATE & SLT

Axiado is building the future of AI powered digital infrastructure. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management. Our technology protects the world’s most critical infrastructure—from data centers to next generation cloud and AI platforms—by securing systems at the foundation levels of hardware, independent of host CPUs and operating systems.

Founded in 2019 and now over 150 employees are strong, Axiado has evolved into a recognized leader in the convergence of AI, security, and silicon innovation. We partner with and are actively engaged in commercial programs with multiple Tier 1 industry leaders, validating both our technology and our long-term market trajectory. Axiado has also won numerous industry awards for our ground-breaking products and technological innovations, including being named one of Fast Company’s 2025 Top 10 Most Innovative Companies in Security, winning the 2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliance’s 2025 “Start-Up to Watch” award.

At Axiado, developing breakthrough technology takes more than great engineering—it takes a team of exceptional people who collaborate boldly, challenge assumptions, and take pride in building what comes next. We value curiosity, execution, respect, and a shared desire to make a meaningful impact on the security and reliability of the digital world.

If you’re driven to innovate, energized by hard problems, and excited to help define the future of secure AI infrastructure, we invite you to apply and join us on this journey.

Axiado Corporation is seeking a Silicon Test Engineer with strong expertise in Automated Test Equipment (ATE) and System-Level Testing (SLT) to join our team. In this role, you will drive New Product Introduction (NPI) from early silicon bring-up through mass production, collaborating with a global, cross-functional team spanning design, test, foundry, and reliability. This position requires both deep technical capability and strong execution skills to successfully deliver across multiple concurrent programs.

Responsibilities

Develop, debug, and optimize ATE and SLT test programs for silicon validation and production.; Work closely with design, product, and validation teams to define and implement comprehensive test requirements.; Analyze test data to improve yield, performance, and reliability.; Develop and maintain test patterns and test methodologies for different device types.; Support JTAG, scan, boundary scan, MBIST and other digital/analog test interfaces.; Collaborate with hardware and firmware teams to ensure robust test coverage and effective failure debug.; Automate test data collection, analysis, and reporting to improve efficiency and scalability.; Provide failure analysis and debug support for both production and engineering samples.; Support new product introduction (NPI) and drive continuous improvement in test coverage, test time, and overall test efficiency.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering or a related discipline.; 5+ years of industry experience in semiconductor test engineering.; Hands-on experience with ATE platforms (e.g., Advantest).; Experience with System-Level Testing (SLT), functional testing, and system-level debug.; Proficiency in programming and scripting for test development (e.g., Python, C/C++, or equivalent).; Strong understanding of semiconductor test methodologies, test coverage, and data analysis.; Familiarity with JTAG, boundary scan, and protocols such as I2C, SPI, eMMC, USB, Ethernet, PCIe, and similar interfaces.; Experience in failure analysis, yield improvement, and test optimization.; Excellent debugging, analytical, and problem-solving skills.; Experience with data visualization tools for test analysis.; Working knowledge of Confluence and JIRA.