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Sr. Staff Digital Engineer

Renesas Electronics Zhubei, Taiwan
Vollzeit Arbeit vor Ort

Veröffentlichungsdatum: 19.10.2026

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

We are looking for a digital design engineer with DFT capabilities

Requirements

Experience: 5+ years of hands-on experience in DFT architecture and implementation for SoC/ASIC.; Skilled in different types of DFT structures, including scan (Stuck-At, At-Speed, Path-Delay), scan compression, boundary scan and MBIST.; Experience in creating and implementing hierarchical DFT architecture in complex SoC.; Experience in Low-Power DFT and MBIST.; Experience in test time and test coverage analysis for scan and MBIST patterns.; Experience in working with test engineering team to bring up production test program.; Extensive knowledge of timing concepts and constraint development.; Experience in developing scan ATPG and MBIST test benches and simulation in pre/post-layout environments.; Experience in RTL is required.
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