Sr Test Engineer

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

We are seeking an experienced and strategic Sr Test Engineer to lead our test engineering initiatives in Hukou location. The ideal candidate will not only possess expert-level skills in ATE test program development but also drive test strategy, DfT (Design for Testability) implementation, and technical mentorship for the team.

2. Experience

- 8-10+ years of hands-on experience in semiconductor test development, with a proven track record of delivering complex mixed-signal/power management products to mass production.

3. Tester Platform Understanding

- Cohu DMDx , DMDx DxV , Acco STS8300 Tester Platform Deep understanding of architecture, resource constraints, and advanced instrument capability are required. Ability to optimize compiler/OS interactions. (Nice to have : Teradyne ETS-800 platform)

4. Advanced Programming Skills

- Mastery of C/C++ and VB. Experience in developing scalable test libraries, drivers, and automation frameworks rather than just single-product test programs.

5. Strategic & Analytical Skills

- Strong capability in statistical data analysis (JMP, Datapower, Galaxy, Dana).
- Experience with GaN (Gallium Nitride) or high-voltage power device testing is highly required .

Responsibilities

Test Architecture & Strategy: Define and architect cost-effective and high-efficiency test solutions for Gate drivers, Power Stages and Isolators products on Cohu DMDx, DMDx DxV and Acco STS8300 platforms.; Advanced Hardware Engineering: Lead the design reviews of complex high-performance test interface hardware (Load board, Probe Card). Solve signal integrity and thermal challenges for high-voltage/high-power (GaN) applications.; NPI Test Leadership: Drive test build for NPI projects from concept to release. Drive DfT (Design for Testability) discussions with IC Design teams during the pre-silicon phase to ensure test coverage and yield targets. Also, together with Silicon Validation team, achieve characterization completion by ATE portion.; Yield & Cost Optimization: Drive systematic yield improvement through advanced statistical data analysis. Formulate and execute aggressive Test Time Reduction (TTR) strategies to significantly lower the Cost of Test (CoT).; Excellent communication , teamwork, and interpersonal skills, act as the technical focal point for cross-functional collaboration with international Designer, PE, and OSATs.

Requirements

Bachelor's degree in Electrical Engineering, Electronics, or related field (Master’s degree strongly preferred ).

Nice to have

Design for Test (DfT): Deep knowledge of Scan, MBIST, and analog DfT techniques.; Automation: Expert in scripting (Python/Perl) to automate data extraction, report generation, or hardware validation flows.; PCB Design: Advanced proficiency in reviewing complex multi-layer PCB designs for high-speed/high-power applications (Altium/Cadence).