Staff Analog Engineer

Key Performance Measures

- Deliver high-quality verification plans, environments, tests, checkers, and coverage within agreed project schedules.
- Identify verification risks, communicate issues promptly, and contribute to effective mitigation plans.
- Achieve verification completeness against approved specifications and coverage goals.
- Develop reusable verification components and improve verification efficiency.
- Provide clear technical documentation and share relevant knowledge with the verification team.
- Collaborate effectively with design, systems, test, validation, and other verification engineers.
- Demonstrate the Spirit of Renesas in all aspects of work.

General

- Concise and proactive communication skills within a multi-site and multi-cultural environment
- Ability to communicate technical recommendations clearly and build alignment based on technical facts.
- Ability to support technical discussions with internal stakeholders, customers, or partners when required.
- Takes responsibility for solutions and makes them happen, self-motivated.
- Looks for continuous improvement in own and Renesas work practices.
- Good analytical and problem-solving skills.
- Results-oriented and able to deliver on-time under tight schedule pressure.
- Ability to propose innovative solutions.
- Cross cultural awareness and sensitivity

Responsibilities

Execute and own assigned design verification activities that support first-pass silicon success and confirm compliance with performance, power, and schedule requirements.; Own or contribute to analog and mixed-signal verification of integrated circuits or subsystems.; Collaborate with AMS DV team members and local contract DV resources on assigned verification activities.; Contribute to verification strategies for mixed-signal IPs and implement verification IP using object-oriented programming principles and methodologies, including UVM.; Verification planning, maintenance, feature extraction, verification tests, coverage and checker development.; Develop efficient, reusable state-of-the-art verification environments and testbench structures.; Participate in technical reviews with analog and digital design, systems, test, validation, and verification teams.; Able to debug the RTL for design intent and interface with cross-functional teams and collaboration in all verification related activities.; Provide technical guidance and support to verification team members within assigned areas of expertise.

Requirements

The ideal candidate has an experience of 5+ years in advanced verification methodologies, owning the verification of complex digital and mixed signal designs; Degree level qualification in electrical engineering, electronics, computer engineering, computer science, or equivalent.; Strong fundamentals in analog and mixed signal circuit concepts and topologies.; Experience working with mixed signal verification environment, simulation, and regression tools such as Cadence Virutuoso, xCelium, Incisive, vManager, IMC; Ability to read analog schematics and extract related main functionality.; Familiar with Verilog based RTL coding and ASIC design methodology.; Strong proficiency in SystemVerilog and advanced verification methodologies, including assertions, constrained randomization, metric-driven verification, and UVM.; Familiar with behavioral modelling of analog blocks using System Verilog (RNM) and VerilogAMS.; Experience in modelling mixed signal blocks including biasing networks, power regulators, bandgaps, simple amplifiers, comparators, data converters, mixers, multiplexers, switches, power converters, etc.; Experience modelling power converters is desired.; Good knowledge of UNIX shell scripting, Perl and TCL scripting.; Proven experience in writing verification plans and test bench development, simulation and debugging.