Staff Engineer, ASIC Development Engineering (Physical Design, Pnr, Floor Planning)

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.

Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.

Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.

Position Overview

We are seeking a highly skilled and experienced Senior Engineer for our PNR function. The successful candidate will be part to a team of talented engineers responsible for ensuring the PNR convergence of our complex semiconductor designs. This role requires a deep understanding of PNR methodologies, leadership skills, and a strategic vision to drive continuous improvement in our PNR processes.

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Responsibilities

Subsystem/block level ownership of Floorplanning, place and route flow for low power, high performance designs, debug of timing/power/area issues, clock tree analysis and assisting full chip timing convergence and timing closure.; Collaborate with cross-function teams, including design, DFT to streamline PNR process; Drive IP integration strategies that ensure quality ASICs and avoid schedule surprises.; Conduct thorough design and timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design convergence.; Stay abreast of industry trends and emerging technologies in PNR and related fields, and incorporate best practices into the team’s workflow.; Prepare and present detailed analysis, reports and technical documentation to stakeholders; Foster a culture of innovation, collaboration, and continuous improvement within the PNR team.

Requirements

A minimum of 5 years of experience in Place and Route Domain.; Proven track record of successfully executing PNR; In-depth knowledge of PNR tools (e.g., Synopsys Fusion Compiler, Cadence Innovus) and methodologies.; Strong understanding of digital design principles, physical design, and semiconductor fabrication processes.; Excellent problem-solving skills and the ability to think strategically and analytically.; Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.; Ability to prioritize tasks and manage multiple project work simultaneously.; A proactive, results-oriented mindset with a passion for innovation and continuous improvement.; Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable.