Staff/ Sr Staff Engineer, Physical Design

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

Experience: 7-10 years

Role Summary

We are seeking an experienced Physical Design Engineer with strong debug skills in Synthesis, UPF, VCLP, LEC to join our semiconductor backend team. The role focuses on RTL synthesis ownership, LEC closure, UPF development, and VCLP sign‑off for complex SoC designs, working closely with Physical Design, DFT, and Front‑End teams.

Responsibilities

Own RTL synthesis from elaboration to final sign‑off.; Develop and debug design constraints and support DFT insertion.; Understand Physical design cycle and different handshaking across teams.; Perform and close logic equivalence checks (LEC) across RTL, synthesized, and ECO netlists.; Create, maintain, and debug UPF, ensuring alignment with FE power intent.; Define and manage power domains (power switches, isolation, retention, always‑on).; Support low‑power sign‑off (VCLP / power checks).; Handle RTL ECOs during late design stages.; Automate flows using TCL scripting.

Requirements

4+ years of hands‑on experience in Physical design for SoC designs.; Strong knowledge of RTL, synthesis optimization, and low‑power design.; Hands‑on experience with UPF creation and power‑domain modelling.; Experience with tools such as Cadence Genus, Synopsys Fusion Compiler, Conformal, VCLP.; Strong TCL scripting skills (Perl/Python is a plus).

Nice to have

Advanced node experience (7nm / 5nm or below).; Power‑aware ECO experience.; Exposure to physical‑aware synthesis.; Ownership of subsystem or SoC‑level UPF.