System Validation engineer (系统验证工程师)

Senior Validation Engineer for DDR memory buffer products, responsible for component-level validation, system debug, and customer issue resolution. This role will work closely with FAE, design, and product teams to validate silicon, debug issues on systems, and support product readiness for mass production.

Responsibilities

Work closely with FAE to provide timely technical support and drive customer issue resolution.; Debug issues on internal and customer systems, reproduce failures and identify root cause.; Develop validation test plans, test cases, and debug methods for new products.; Lead component-level validation and characterization for DDR memory buffer products.; Analyze electrical, functional, and timing behavior using lab equipment and system test platforms.; Collaborate with Design, Product Engineering, and Quality teams to resolve validation issues.

Requirements

MS/BS in Electrical Engineering, Electronics Engineering, or a related field.; 3+ years of experience in semiconductor validation, product engineering, applications engineering, or system-level debug.; Familiarity with x86 systems and platform-level bring-up/debug.; Experience in high-speed interface or memory-related projects, such as SerDes, PCIe, RCD, DRAM, DIMM, or DDR memory subsystems.; Strong written and verbal communication skills, with experience working cross-functionally with FAE, design, and customers.; Hands-on experience with lab equipment such as oscilloscopes, logic analyzers, protocol analyzers, and related debug tools.; Ability to debug issues at component, board, and system level.