Associate Hardware Engineer

FIPV (Foundation IP Development VN) is responsible for the design, development, verification, and release of Foundation IP hard macros, IO libraries, and power-related IPs used in advanced semiconductor products.

This role covers activities from specification understanding through circuit design, physical layout, characterization cell/IP to generate timing, power and electrical behavior models, and chip-top integration support. The engineer will contribute to delivering high-quality IP solutions that enable successful product development across advanced technology nodes.

Responsibilities

Develop and optimize custom layout implementations for IO (GPIO, Peripheral IO), Power, and Hard Macro IPs on advanced semiconductor technologies (e.g. TSMC, GlobalFoundries...), working closely with technical experts from both Japan and Vietnam teams.; Perform full-custom layout design for IO circuits, analog circuits, and low-power control circuits from schematic implementation through final layout release, ensuring compliance with IP specifications and quality requirements.; Conduct floorplan, device placement, routing, and layout optimization of hierarchical IP blocks while adhering to technology design rules, quality assurance standards, and manufacturability requirements.; Ensure designs achieve targets for performance, power, area, reliability, ESD robustness, and silicon manufacturability.; Execute physical verification activities including DRC, LVS, ERC, Antenna, and related validation checks, and perform root-cause analysis and debugging of verification issues.; Generate and maintain IP deliverables and library collateral, including GDSII, CDL, LEF, Liberty, NDM, and associated documentation required for downstream implementation flows.; Collaborate with Chip Top, Product, and Physical Design teams to support integration, verification, and PPA (Performance, Power, Area) optimization at the chip level.; Analyze and address reliability concerns, including ESD, Electromigration (EM), IR Drop, and Latch-up, throughout the IP development cycle.; Drive productivity and quality improvements through methodology enhancement, automation development, and continuous process optimization.

Requirements

Bachelor’s degree in Electronics Engineering, Electrical Engineering, Microelectronics, Computer Engineering, or related fields.; Strong Academic background in semiconductor devices, ability to understand and analyze the physical behavior of CMOS circuits, parasitic effects, signal propagation, power distribution, and ESD protection mechanisms is highly desirable.; Strong foundation in engineering physics and mathematics. Familiar with fundamental concepts such as Ohm's Law, Kirchhoff's Current and Voltage Laws (KCL/KVL), current flow, voltage, resistance, capacitance, and basic semiconductor physics.; Demonstrated interest in semiconductor IP development, including circuit design, physical implementation, characterization, library development, and chip integration.; Familiarity with EDA tools is a plus (Cadence Virtuoso, Synopsys, Siemens/Mentor, etc.).; Knowledge of Linux/Unix operating systems and scripting languages (Shell, Python, Perl, Tcl) is an advantage.; Strong analytical and problem-solving skills.; Willingness to learn advanced semiconductor technologies and design methodologies.; Good communication and teamwork skills in a multicultural environment.; Ability to work independently as well as collaboratively within global engineering teams.; Good English reading and communication skills.