DDR Interface Evaluation Leader

【Background of the Recruitment】

As automotive electrification and intelligence continue to advance, automotive SoCs have become a core technology that directly supports vehicle performance and functionality.

The R-Car series has evolved as a large-scale automotive SoC through the advanced integration of a wide range of IPs, including CPU, high‑speed interfaces, memory, AI/video, functional safety, and security.

Within such SoCs, the DDR interface is a critical component that directly impacts system stability and performance.

Ensuring reliable operation through silicon‑level evaluation, margin analysis, and stress testing is essential, particularly as SoCs become more highly integrated and operate at higher performance levels.

We are therefore seeking a technical leader who can leverage hands‑on experience in DDR interface evaluation to work closely with design teams and IP vendors, and lead evaluation activities with sound technical judgment.

This role is expected to contribute to overall development by using evaluation as a starting point to support quality improvement across the SoC.

【Job Description】

※The full details regarding your position scope as well as any future potential changes in work location and job scope will be provided during the interview process.

【WANT】

- Experience leading or co‑leading evaluation activities for DDR PHY, memory controllers, or board‑level DDR interfaces.
- Experience in measurement and analysis of DDR signals, timing, and power behavior using lab equipment (e.g., oscilloscopes, logic analyzers).
- Experience coordinating with external IP vendors on technical inquiries, issue alignment, and sharing of evaluation results.
- Experience in automotive SoC projects or in products requiring high levels of quality and reliability.
- Interest in expanding contribution beyond DDR evaluation into broader cross‑functional collaboration with design and SoC teams.
- Japanese language proficiency at a conversational level

Responsibilities

Lead the technical execution of DDR interface evaluation for automotive SoCs (R-Car series). - Target examples include LPDDR4X / 5 / 5X / 6, DDR PHY, and memory‑controller‑related interfaces.; Drive silicon and board‑level evaluation, margin analysis, stress testing, and compliance with standards and internal guidelines, ensuring the quality and reliability of the DDR interface.; Define and align evaluation strategy, design test items and conditions, and consolidate evaluation results into clear outputs.; When issues arise, collaborate with design teams, SoC teams, and IP vendors to perform root‑cause analysis and drive countermeasure planning.; Provide technical leadership to evaluation and design members across Japan, India, and Vietnam, clarifying evaluation flow and decision criteria to improve overall quality.

Requirements

Hands‑on experience in evaluation or verification of DDR interfaces (e.g., LPDDR4/4X/5).; Experience in issue analysis, root‑cause investigation, and countermeasure discussion based on margin testing and stress evaluation.; Ability to organize evaluation results and conduct technical discussions and alignment with design teams and stakeholders.; Knowledge or experience related to analog behavior and characteristics relevant to DDR interfaces (e.g., DDR PHY, PLL, jitter, noise, SI/PI, power integrity).; Ability to collaborate technically in English with design sites in India and Vietnam, as well as IP vendors.