Design Verification Intern

Summer Internship - May - Aug, 2027

Duluth, GA - Hybrid 3 days per week

Must be currently enrolled full time in a university degree program pursing a bachelor, master, or PhD degree. (MSEE preferred) Must not have graduated before September 2027.

Renesas is looking for a talented individual for their memory interface products. These memory interface products mainly go to datacenters for AI and cloud computing, providing the highest bandwidth for intensive computing while consuming low power. This exciting role is responsible for the development of digital sections of leading-edge memory data buffer chips for DDR5, DDR6 and beyond.

Responsibilities

Verification of DDR5 Data Buffer to meet functional and performance specifications.; Be able to integrate and test on System-level and block level using UVM methodology; Support in developing verification plan based on specifications.; Support in Verification planning, maintenance, feature extraction, verification tests, coverage and checker development.; Develop efficient, reusable state-of-the-art verification environments and testbench structures.; Optimize solutions for key indicators such as reusability, performance and ease of use; Identify and communicate improvements that may ease verification and/or improve design behavior.; Support in optimizing UVM based testbench.; Drive the Memory interface products verification effort, including defining the verification strategy, developing test plans, coverage, and executing tests.; Drive and quality control the creation of a verification test plan.; Work closely with the design team to ensure that the design meets the requirements and is testable.; Identify and drive improvements to the verification process to ensure the highest levels of quality and efficiency.; Drive and monitor coverage of design verification.; Provide regular updates to management on the status of the verification effort.

Requirements

Must be currently enrolled full time in a university degree program pursing a bachelor, master, or PhD degree. (MSEE preferred) Must not have graduated before September 2027.; Familiar with at least one coding language: Verilog, System Verilog, UVM concepts.; Strong problem-solving abilities.; Must have good written and verbal cross-functional communication skills.; Must be a team player and yet be an independent thinker with strong design fundamentals.