Hardware Engineer, Performance Modeling

Normal is an applied AI company building foundational hardware and software for the semiconductor industry and critical AI infrastructure. As a Performance Modeling Engineer, you will build the transaction-level model (TLM) of Normal's physics-inspired ASICs, correlate it against RTL, FPGA prototypes, and synthesis results, and work closely with the architecture, hardware design and DV teams. Hybrid: 3 days a week in the office, in Mountain View, New York or London.

Responsibilities

Build and maintain a cycle-accurate approximate transaction-level model (TLM) of compute tiles, memory hierarchy, and interconnect; Translate TLM and RTL results combined with physical design into calibrated parameters (latency, bandwidth, energy, utilization, occupancy) for end-to-end system performance prediction on AI workloads; Provide the TLM as a reference golden model for DV, including transaction-level scoreboards and performance checks; Plan modeling work against the hardware roadmap and run sensitivity studies on key hardware parameters to give architecture and hardware teams clear recommendations

Requirements

5+ years of experience in performance modeling at a major semiconductor company; Demonstrated proficiency in understanding architectures and transforming that to performant modeling code; Use of various modeling techniques and languages; Excellent written and spoken communication skills

Nice to have

Experience with AI acceleration hardware; Experience with architecture-level modeling and cost tools such as AccelForge, Timeloop/Accelergy, CACTI, McPAT, or gem5; Experience with DV methodology; Hands-on use of LLMs or agentic tools in development workflows; Exposure to analog, mixed-signal, or unconventional compute; Experience with memory interfaces (LPDDR, HBM, DDR) and other I/O