Memory Layout Technical Lead

Layout design for non-volatile memory (NVM) IP, including Flash, MRAM, and ReRAM, for MCUs targeting automotive, industrial, and IoT applications. The role involves layout design for NVM IP based on memory cells developed by in-house fabs and foundry partners, contributing to PPA (Performance, Power, and Area) optimization of MCU products, and collaborating with global NVM development teams in Japan and overseas. The position is responsible for the layout design of embedded NVM IP for future MCUs, as part of Renesas' investment in next-generation embedded NVM technologies and IP development.

Responsibilities

Serve as the technical lead for the memory layout design team; Develop layout strategies based on IP requirements and circuit specifications; Lead hands-on layout design and verification activities

Requirements

Experience in full-custom layout design for non-volatile memory (typically 10+ years); Experience in building consensus with circuit designers and leading layout design reviews (typically 5+ years); Experience collaborating with overseas partners in English

Nice to have

Experience in P&R design; Experience in analog circuit design; Experience in AI-assisted layout design

Benefits

Competitive compensation system; Comprehensive benefits (details provided during the selection process)