Principal Engineer- Design Verification

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

Job Summary

We are seeking a highly experienced Verification Lead to drive the verification strategy and execution for next-generation UA Link Switch products within the Memory Interface Division (MID) . The candidate will be responsible for leading verification efforts across complex digital subsystems and SoCs, ensuring first-silicon success for high-performance, high-bandwidth interconnect and switching solutions.

The ideal candidate will possess deep expertise in modern verification methodologies and extensive experience verifying large-scale, high-speed digital designs involving switching fabrics, SerDes-based interfaces, memory subsystems, and complex SoC architectures.

Responsibilities

Define and own the verification strategy, methodology, and execution plan for UA Link Switch products.; Lead verification architecture, testbench development, coverage planning, and verification closure activities.; Build and drive scalable UVM/ System Verilog-based verification environments for complex SoC and subsystem designs.; Collaborate closely with architecture, design, firmware, system validation, and silicon bring-up teams to ensure comprehensive verification coverage.; Develop verification plans covering functionality, performance, reliability, error handling, and corner-case scenarios.; Drive debug and root-cause analysis of design and verification issues.; Define and track verification metrics including functional coverage, code coverage, assertions, and regression quality.; Lead verification reviews, sign-off activities, and silicon readiness assessments.; Mentor verification engineers and establish best practices across the organization.

Requirements

Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related field.; 18+ years of experience in ASIC/SoC verification.; Proven leadership experience delivering complex SoC or subsystem verification programs from architecture through tape-out.; Strong expertise in:; System Verilog, UVM, Assertion-Based Verification (SVA), Functional and Code Coverage Methodologies, Simulation and Regression Infrastructure and Verification Closure Techniques.; Experience verifying large-scale digital systems involving:; High-speed digital designs, SoCs and subsystem integration, Switching fabrics and interconnect architectures, Memory controllers and memory subsystems and Microcontroller-based systems.; Strong understanding of RTL design concepts and hardware architecture.; Demonstrated ability to drive cross-functional technical teams and influence architecture and design decisions.

Nice to have

Prior verification experience in one or more of the following:; High-speed SerDes-based systems; Switching fabrics and packet-based architectures; Memory interface technologies; AI/HPC interconnect solutions; PCIe, CXL, Ethernet, UALink, UCIe, or similar protocols; Experience with formal verification, emulation, and FPGA prototyping.; Familiarity with performance verification and system-level validation methodologies.; Experience debugging silicon issues and supporting post-silicon validation.; Hands-on experience with mixed hardware/firmware verification environments.; Experience leading geographically distributed verification teams.