Principal Engineer, STA & Synthesis

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

We are seeking a Principal Engineer – Implementation Lead to own synthesis and timing closure sign-off for low-power, chiplet-based MCU designs implemented on cost-optimized mature process nodes. This role is critical for ensuring design quality and convergence while meeting power, performance, and cost targets.

Responsibilities

Drive RTL-to-gate synthesis for complex multi-die MCU designs using industry-standard tools; Optimize for timing, power, and area while adhering to mature-node constraints; Lead static timing analysis (STA) and timing closure activities across multiple corners and modes; Ensure sign-off compliance for timing, power, and signal integrity; Work closely with RTL, DFT, and physical design teams to resolve timing issues; Own full chip constraints and design optimizations to achieve convergence; Define and maintain synthesis and timing closure methodologies tailored for cost-sensitive MCU designs; Evaluate EDA tools and flows for improved efficiency and turnaround time

Requirements

BTech/MTech in Electrical/Electronic Engineering, Computer Engineering or Computer Science with 15+ years of experience in ASIC/SoC implementation; Proven experience in mature-node technologies (e.g., 22nm, 12nm) and low-power design strategies and multi-clock domain designs; Expertise in Synopsys/Cadence synthesis tools and STA tools; Expertise in multi-mode, multi-corner timing analysis and constraint management; Experience in timing closure of external interfaces like SPI/I2C/Ethernet/CAN; Experience with hierarchical timing closure; Experience with UPF/CPF-based power intent and low-power optimization techniques (clock gating, multi-voltage domains).; Extensive experience with ECO flows for timing fixes and late-stage design changes; Strong scripting skills (Tcl, Perl, Python) for automation of synthesis and STA flows; Experience with timing sign-off for chiplet-based designs is a strong plus; Strong communication skills (written and verbal), problem solving, teamwork, attention to detail, commitment to task, and quality focus; Can – do attitude, openness to new environment, people and culture; Ability to propose innovative and leading edge solutions; Strong drive & ability to coordinate work across highly experienced global teams