Principal ESD Engineer

• Renesas is seeking a recognized ESD expert to drive ESD methodology, IP development, and sign-off verification for advanced semiconductor products, including FinFET technologies and high-speed interfaces.

Responsibilities

Lead ESD architecture development for advanced-node semiconductor products.; Design and optimize custom ESD protection devices, clamps, and ESD IP solutions.; Provide co-design support to maximize both performance and ESD protection robustness.; Lead ESD sign-off reviews and risk assessments for complex SoCs and mixed-signal products.; Develop and maintain automated ESD verification methodologies and flows.; Support silicon characterization using HBM, CDM, TLP, VF-TLP, and Latch-Up testing.; Drive root-cause analysis of ESD-related failures and implement corrective actions.; Collaborate with foundries, EDA vendors, and internal design teams.

Requirements

M.S. or Ph.D. in Electrical Engineering or related field.; 10+ years of semiconductor ESD design experience.; Strong knowledge of: ESD device physics, HBM, CDM, TLP, VF-TLP, Latch-Up, Advanced CMOS and FinFET technologies.; Hands-on experience with ESD protection design for FinFET SoCs and SerDes products.; Hands-on experience in ESD cell design and custom ESD IP development.; Strong knowledge of ESD sign-off methodologies and verification techniques.; Experience with Calibre PERC or equivalent ESD verification tools.; Proven ability to develop and deploy ESD methodologies across multiple product families and technology nodes.; Demonstrated leadership experience in complex cross-functional engineering environments.; Strong initiative, collaboration, and ownership, with a proven track record of driving results under aggressive timelines.; Strong technical writing skills with the ability to produce clear technical reports, design reviews, and engineering recommendations.; Strong communication skills with the ability to effectively communicate technical risks, recommendations, and methodologies across global teams including Japan, Europe and Asia.

Nice to have

Hands-on experience developing and maintaining Calibre PERC rule decks.; Experience supporting advanced-node AI, HPC, networking, memory, or data-center products.; Experience with IEC/EMC or system-level ESD considerations.