Senior ATE and SLT Test Engineer

About Axiado

Axiado is redefining how AI infrastructure gets secured and managed. Founded in 2019, we’re a fast-growing, well-funded team of over 180 people worldwide, building the Trusted Control/Compute Unit (TCU), a new class of semiconductor that integrates hardware security, real-time platform management, and AI-driven optimization. Our TCU-based Platform Efficiency Controller is shipping hardware that makes AI servers measurably more efficient, more secure, and more reliable, and we’re extending that foundation into a hardware-anchored management fabric that scales from a single board to the whole fleet.

Backed by strong funding and validated by commercial programs with Tier 1 industry leaders, Axiado has earned recognition through numerous industry awards, including the 2026 AI in Cybersecurity Innovation Award from TMCnet, a Diamond award for Zero Trust Solution of the Year at the 2026 Pinnacle Awards, and Gold at the 2026 Cybersecurity Excellence Awards for AI Security Solution, as well as being a finalist for the Start-Up to Watch Award from the Global Semiconductor Alliance. We’re small enough that every person’s work visibly shapes the company, and we look for people who want to build, not just execute. Every employee holds equity, meaning your work directly builds your stake in the company’s future, not just a paycheck. If you want to help define what comes next, let’s talk.

About the Role

Axiado Corporation is seeking a Silicon Test Engineer with strong expertise in Automated Test Equipment (ATE) and System-Level Testing (SLT) to join our team. In this role, you will drive New Product Introduction (NPI) from early silicon bring-up through mass production, collaborating with a global, cross-functional team spanning design, test, foundry, and reliability. This position requires both deep technical capability and strong execution skills to successfully deliver across multiple concurrent programs.

Responsibilities

Develop, debug, and optimize ATE and SLT test programs for silicon validation and production.; Work closely with design, product, and validation teams to define and implement comprehensive test requirements.; Analyze test data to improve yield, performance, and reliability.; Develop and maintain test patterns and test methodologies for different device types.; Support JTAG, scan, boundary scan, MBIST and other digital/analog test interfaces.; Collaborate with hardware and firmware teams to ensure robust test coverage and effective failure debug.; Automate test data collection, analysis, and reporting to improve efficiency and scalability.; Provide failure analysis and debug support for both production and engineering samples.; Support new product introduction (NPI) and drive continuous improvement in test coverage, test time, and overall test efficiency.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering or a related discipline.; 5+ years of industry experience in semiconductor test engineering.; Hands-on experience with ATE platforms (e.g., Advantest).; Experience with System-Level Testing (SLT), functional testing, and system-level debug.; Proficiency in programming and scripting for test development (e.g., Python, C/C++, or equivalent).; Strong understanding of semiconductor test methodologies, test coverage, and data analysis.; Familiarity with JTAG, boundary scan, and protocols such as I2C, SPI, eMMC, USB, Ethernet, PCIe, and similar interfaces.; Experience in failure analysis, yield improvement, and test optimization.; Excellent debugging, analytical, and problem-solving skills.; Experience with data visualization tools for test analysis.; Working knowledge of Confluence and JIRA.