Senior Director, Physical Design & Backend Engineering (HPC)

The Senior Director, Physical Design & Backend Engineering is accountable for end-to-end backend execution

across HPC SoC and MCU programs, including implementation, signoff, and convergence from RTL to GDS.

This role leads globally distributed engineering teams and ensures delivery of high-quality silicon on schedule,

meeting defined power, performance, and area (PPA) targets. The role operates at the intersection of execution,

technology enablement, and organizational leadership, driving consistency, scalability, and reliability across

multiple sites and concurrent programs.

Experience

• Approximately 20+ years of experience in semiconductor design, with strong focus on physical design and

implementation.

Technical Expertise

• End-to-end RTL-to-GDSII flow, including synthesis, place and route, timing closure, and physical

verification.

- Advanced node implementation and signoff methodologies.
- Deep understanding of SoC and MCU design and integration.

Leadership Capabilities

- Ability to lead large, globally distributed teams in a matrixed environment.
- Strong execution focus with accountability for delivery outcomes.
- Effective cross-functional collaboration and stakeholder management.
- Data-driven decision-making and structured problem-solving.

Key Success Measures

- On-time delivery of silicon across programs.
- Achievement of PPA and quality targets.
- Improvement in execution predictability and cycle time.
- Organizational scalability and capability development.

Responsibilities

End-to-End Backend Execution; Own full lifecycle delivery from RTL through physical implementation, signoff, and tape-out.; Ensure predictable execution, design closure, and milestone adherence across all programs.; Drive first-pass silicon success through robust methodologies and execution discipline.; Global Team Leadership; Lead and scale large, geographically distributed backend engineering teams.; Establish clear accountability, performance standards, and delivery ownership across sites.; Build organizational capability to support multiple concurrent SoC and MCU programs.; PPA and Quality Accountability; Own delivery against defined power, performance, and area (PPA) targets.; Drive continuous improvement in cost, quality, and engineering efficiency.; Ensure adherence to quality standards, signoff criteria, and validation requirements.; Technology and Methodology Enablement; Enable adoption of advanced process nodes and associated design methodologies.; Drive improvements in tools, flows, and engineering practices across implementation and signoff.; Partner with foundries, EDA vendors, and internal teams to enhance design outcomes.; Cross-Functional Collaboration; Partner with architecture, RTL, DFT, methodology, and product engineering teams.; Ensure alignment between architectural intent and physical implementation feasibility.; Support program execution through close collaboration with program and product leadership.; Organizational Execution and Scaling; Standardize ways of working across global teams to reduce variability and improve predictability.; Drive data-driven execution using metrics, KPIs, and performance tracking.; Identify and remove bottlenecks impacting delivery timelines or quality

Requirements

Proven experience leading large-scale, global engineering teams.; Demonstrated track record of delivering complex SoC programs across multiple technology nodes.

Nice to have

Experience in high-performance computing, automotive, or advanced SoC domains.; Exposure to methodology and flow development at scale.; Experience working across multiple geographies and cultures.