Senior Engineer - ASIC Design

We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies.

Responsibilities

Develop ASIC IP blocks and subsystems, contributing to the advancement of 5G and 6G communication technology; Take full ownership of a design, whether at the block or subsystem level; Generate comprehensive documentation throughout the design lifecycle; Perform digital design and conduct all RTL sign-off checks; Continuously enhance and optimize design methodologies and processes; Collaborate with IP Architects to break down requirements and create detailed IP architecture and design specifications; Work closely with verification engineers to review and refine verification plans; Build competence in the technical domain; Engage in cross-team collaboration to ensure successful project delivery

Requirements

Bachelor’s degree in electrical or computer engineering; 10+ years industry experience in ASIC IP Design; Understanding of ASIC technology, design environments, and methodologies; IP development from concept (High-level Spec) to Micro-architecture, RTL creation and sign-off with SystemVerilog; RTL static sign-off tools such as SpyGlass; Understanding of Synthesis and Timing concepts; Scripting languages like TCL, Python, or similar; AMBA-based IP development using AXI and CHI; SystemVerilog Assertions; Experience with Cadence and Synopsys front-end and middle-end design suites; Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results; High attention to detail and commitment to quality; Strong focus on meeting project deadlines and deliverables; Proficient in English, with strong communication skills

Nice to have

Understanding of radio access systems and their components; Modelling in MATLAB is a plus; Expertise in low-power design, including specifying power intent using UPF or similar standards; Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira); Experience in designing IPs for one or more of the following hardware domains: ARM-based embedded microcontroller systems including their control and interface peripherals (Ethernet, USB, CPRI); Wireless infrastructure specific protocols and interfaces and protocols; Implementation of hardware-based digital signal processing systems (filters, adaptation, knowledge of CFR, DPD, Digital up-conversion and down-conversion chains etc)

Benefits

Creative Freedom; Global Impact; Work-Life Balance; Professional Growth; International work environment; Collaborative and inclusive culture