Джерело: CrawlJobs
Ця вакансія не має повного перекладу вибраною мовою. Нижче показано оригінальний зміст.
Повна зайнятість Робота на місці

Дата публікації: 01.09.2026

As a Signal Integrity / Power Integrity Intern, you will help design and validate the next generation of high-performance AI systems. You will work closely with package, PCB, ASIC, and system engineers to analyze high-speed interfaces, extract channel models, and improve signal quality across our accelerator platforms. This role provides hands-on experience with industry-leading tools and real-world challenges involving PCIe, Ethernet, high-speed SerDes channels, advanced packaging, and multi-board systems.

Responsibilities

Perform channel analysis for high-speed interfaces including PCIe, Ethernet, and other SerDes links; Extract and validate S-parameter models from package and PCB layouts; Analyze insertion loss, return loss, impedance discontinuities, and crosstalk; Generate channel compliance reports and support design reviews; Build and validate 3D electromagnetic models using Ansys HFSS; Develop board and package channel models from ECAD design databases; Correlate simulation results with measurements and lab data; Support mixed package-board channel simulations and optimization; Partner with PCB layout, package, hardware, and ASIC teams to improve signal integrity; Identify root causes of channel degradation and propose design improvements; Contribute to SI design guidelines and best practices

Requirements

Progress toward a BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field; Coursework or project experience in signal integrity, electromagnetics, RF, microwave engineering, or high-speed digital design; Familiarity with transmission line theory and S-parameters; Understanding of PCB stackups, routing, and high-speed design fundamentals; Strong analytical and debugging skills; Excellent communication and collaboration skills

Nice to have

Experience with Ansys HFSS, SIwave, ADS, CST, or similar simulation tools; Experience with PCIe, Ethernet, DDR, or other high-speed interfaces; Familiarity with Allegro, APD, ODB++, IPC2581, or other ECAD databases; Experience processing Touchstone files and channel metrics; Python scripting for simulation automation and data analysis; Experience with laboratory measurements using VNAs, oscilloscopes, or TDR equipment

Benefits

12-week paid internship; Generous housing support for those relocating; Daily lunch and dinner in our office; Direct mentorship from industry leaders and world-class engineers; Opportunity to work on one of the most important problems of our time
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