Sr. Engineer, Design Enablement

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

We’re looking for a Senior Engineer (5+ Years) in design enablement space, with strong RTL and static verification expertise to help build robust design-quality methodologies across our teams.

Requirements

Strong RTL design experience (Verilog/SystemVerilog); Strong hands-on knowledge of Lint, CDC, RDC flows; Tcl and shell scripting; Python (good to have); Ability to debug RTL/static issues and improve design quality; Develop & maintain design enablement methodologies; Drive Lint/CDC/RDC signoff flows; Automate checks and design workflows; Collaborate with design teams to ensure high-quality RTL; Create guidelines and best practices; If you’re passionate about methodology, automation, and enabling high-quality RTL design teams, we’d love to connect!