Staff Analogue Designer, CMOS Modelling

We are looking for a Analogue Designer, CMOS Modelling to join our Cryo-CMOS IC team at IonQ based in our Oxford office. In this role, you will be responsible for owning full-chip mixed-signal CMOS modelling as a first-class part of our Cryo-CMOS development flow. This includes building the behavioural model of the chip that the whole team will simulate against, allowing the team to design, verify and validate the integrated circuits that control our quantum processors - the novel technology that sits at the very heart of our world-leading quantum computers. You will enable the team to work in conditions from room temperature down to a few kelvin. This work will allow the team to meet our research and development goals, contributing directly to our ability to deliver on our technological milestones.

Responsibilities

Own the full-chip modelling strategy, including model architecture, abstraction levels, accuracy targets and sign-off criteria, and implementing across the whole IC development flow; Develop Verilog-A and Verilog-AMS models of analogue blocks (references, DACs, switches, regulators, clock distribution) and assemble them into a simulatable full chip; Build real-number models (SystemVerilog nettype/UDN, legacy wreal) so the full chip runs in digital verification and regression at speed; Derive models from mathematics, for example turn a transfer function, a Z-parameter network description or a MATLAB analysis into robust, convergent Verilog-A with well-behaved tolerances; Define and run model-versus-schematic correlation, to keep models in sync with design releases, and feed measured silicon behaviour back into the flow; Stand up mixed-signal co-simulation and regression (Cadence AMS Designer, Xcelium with Spectre); contribute to block-level design reviews and mentor engineers on modelling craft

Requirements

10+ years of deep analogue and mixed-signal design and modelling experience; expert Verilog-A and Verilog-AMS; strong real-number modelling; ability to derive a model from equations and implement end to end; ability to judge what to model and at what fidelity; ability to align with wider team on what a model does and does not promise; ability to work along designers, verification and system engineers and contribute effectively within a fast moving, highly technical team

Nice to have

working with models used in production tapeout flows; strong mathematical foundations, including experience with linear systems, Laplace and z-domain analysis, network (Z-) parameters, noise and non-linearity; fluency in a production Cadence flow, such as working with simulation environments like Virtuoso, Spectre, Xcelium and AMS Designer or similar; experience working with SystemVerilog, MATLAB or Python/NumPy for analysis and model validation; extreme-environment silicon experience such as, cryogenics and space

Benefits

comprehensive medical, dental, and vision plans; matching 401(k); unlimited PTO and paid holidays; parental/adoption leave; legal insurance; home technology stipend