Staff Engineer - Design Verification

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world

We are looking for a motivated and talented Design Verification Engineer to join our team in creating next-generation Power management solutions.

Responsibilities

Define and own verification plans, methodologies, and coverage strategies for complex SoC designs; Architect and implement verification environments from scratch and enhance existing frameworks; Drive block-level, subsystem-level, and full-chip verification; Build Agents, sequences, drivers, monitors, and scoreboards as part of automation.; Integrate industry-standard VIPs, create custom transactor.; Lead end2end verification, including: Gate level simulations and debugs, coverage analysis and closure, regression, triage failures, and ensure quality sign-off; Mentor junior and mid-level verification engineers; Act as technical lead or owner for key verification deliverables

Requirements

Bachelor's degree in Electrical Engineering or equivalent practical experience.; Overall 12+ years of experience with verification methodology such as universal verification methodology (UVM).; Experience with industry-standard simulators, revision control systems, and regression systems.; Experience with Architecting block the full verification lifecycle.; Excellent problem solving and communication skills.; Construct testbenches components like scoreboard, agents, sequencers, and monitors; Debugging RTL and Gate simulations and working with cross functionals team to verify fixes; Converting verification tests to test patterns and assisting Test Engineers on ATE vector bring up; Experience developing and maintaining verification testbenches, test cases, and test environments.; Understanding of SoC architecture and functionality, Mixed signal designs.; Good knowledge of analog components : ADC, DAC, PLL, Oscilators and PI controllers.; Passion for learning and engineering great solutions; Proven written and verbal communication skills that demonstrate clarity of thought and conviction; Working knowledge of one or more scripting languages (Perl, Python) and ability to use them to automate/accelerate verification and analysis tasks; Experience of directed and constrained random verification methodology Good knowledge in UVM, Verilog, SV, C/C++, Shell, Python; Strong debug, logical thinking and analytical skills