Staff/ Sr Staff/Principal Engineer, STA

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

We are seeking a seasoned Backend Design Expert specializing in Static Timing Analysis (STA) and Logic Synthesis . You will own the RTL-to-Gate conversion, constraint development, and final timing closure, ensuring our chips deliver maximum performance at the lowest possible power and area.

Responsibilities

Physical-Aware Synthesis and PPA optimization: Own and execute hierarchical synthesis flows to translate SystemVerilog RTL into optimized gate-level netlists. Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout congestion and achieve PPA targets, identify bottlenecks and drive optimizations (e.g., critical path restructuring, datapath optimization). Conduct flat and hierarchical synthesis, ensuring seamless interface timing budgets. Manage formal verification (LEC) to ensure logical equivalence between RTL and netlist. UPF management for multiply power domains.; Timing Closure & STA: Perform block-level and full-chip STA across multi-mode and multi-corner (MMMC) scenarios using industry-standard tools. Collaborate with PNR team, understand the clock tree and provide timely feedback to optimize the clock tree and achieve best QOR and perform STA signoff checks to closure.; Constraint Development: Architect, validate, and manage files, addressing both functional and DFT modes. Develop and manage comprehensive block-level and top-level constraints (SDC / UPF).; Low-Power Implementation: Implement and verify UPF-based (Unified Power Format) low-power architectures and multi-voltage domains; Programming/Scripting: Strong scripting skills in Tcl, Python, or Perl to automate flows and improve design methodologies

Requirements

Experience of about 8-15 years in synthesis and STA closure.; Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.; Ability to understand design specifications, can contribute to design planning, partitioning, and setup a feasible seed for convergence PD cycle.; Extensive experience in STA closure on complex design with ability to understand the clocks structure from both functional and DFT side and provide solutions to complete design closure.; Worked on synthesis of high frequency designs and come up PPA solutions to meet the targets.; Good understanding of EDA tools such as Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC.; Strong understanding of static timing analysis, power analysis, and signal integrity analysis.; Excellent problem-solving skills and attention to detail.; Excellent scripting skills and development of utilities to reduce overall TAT.; Ability to work effectively in a team environment and communicate clearly with cross-functional teams.; Experience in mentoring and coaching junior engineers is a plus.