Technologist, Mask Design Engineering

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.

Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.

Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.

Responsibilities

Layout Design & Optimization: Develop and optimize peripheral and core circuit layouts for Analog, Digital, and Mixed-signal domains, ensuring adherence to design specifications, performance requirements, and foundry rules.; Design Verification: Perform DRC (Design Rule Check) and LVS (Layout Versus Schematic) verification, parasitic extraction, and sign-off methodologies to guarantee design integrity and first-pass success.; Power Distribution & Floorplanning: Analyze and implement full-chip power distribution strategies and floorplanning optimization to ensure efficient electrical performance, minimize parasitics, and reduce die size.; Cross-Functional Collaboration: Work closely with design and process engineering teams across multiple sites to resolve issues, align methodologies, and drive project success while maintaining high standards of accuracy and consistency.

Requirements

Extensive IC Layout Design: Over 14 years of proven expertise in custom full-chip layouts across analog, digital, and mixed-signal domains, with deep understanding of power distribution and signal planning.; Tool Proficiency: Highly skilled in industry-standard layout verification tools (DRC/LVS, parasitic extraction, and sign-off methodologies).; Floorplanning Expertise: Strong background in floorplanning strategies and placement optimization to minimize parasitics and reduce die size using a correct-by-construction approach.; Cross-Functional Collaboration: Adept at working with multi-site, cross-disciplinary teams and managing small teams to drive project success.; Communication & Methodology: Strong verbal and written communication skills with knowledge of layout automation techniques and a proactive mindset toward continuous improvement and efficiency.