Compiler Backend Engineer

Normal's hardware runs the most memory-bound parts of large-model inference inside memory itself, rather than shuttling weights to a processor. The software that makes this programmable doesn't exist yet in any standard form. As a Compiler Engineer focused on the backend, you will help design and build the custom compilation that maps LLM inference onto it, from scheduling and memory planning to the code our hardware actually executes. You will work at the boundary between the compiler and the hardware. Our chip is pre-silicon, so you will measure your work against our simulators and FPGA prototypes first, and against silicon as it arrives.

Responsibilities

Code Generation: Build the passes that turn lowered programs into the code our hardware executes, designing new compilation approaches where conventional ones don't fit; Scheduling and Memory Planning: Own how work and data are scheduled and placed across hardware resources, measured by utilization and end-to-end latency on LLM inference; Fusion and Dispatch: Own fusion and dispatch decisions for LLM inference, so the hardware spends its time computing rather than moving data; Hardware Co-Design: Work the abstraction layer between the compiler and the hardware, and feed compiler constraints back to hardware architects while the design can still change; Profiling and Validation: Validate every optimization with measured results from simulators, FPGA prototypes, and then silicon, and maintain a performance regression suite; Cross-Team Handoffs: Take lowered programs from frontend compiler engineers, and decide with the team which operations the compiler generates and which use hand-tuned kernels

Requirements

Deep experience with compiler optimization or code generation for accelerators or other non-CPU targets: scheduling, tiling, fusion, or resource allocation; Comfort working close to hardware: thinking in terms of memory bandwidth and utilization as well as asymptotic complexity; Willingness to design compilation approaches from first principles when existing ones don't fit the hardware; Track record of shipping optimizations that moved a measured performance number; Comfort building software for hardware that is still evolving, from simulation through bring-up; Fluency in Python, and familiarity with C, C++, or Rust

Nice to have

Experience with PyTorch's compilation stack (TorchDynamo, FX, Inductor, torch.export) or other ML compilers, such as IREE, TVM, or XLA; Experience compiling for in-memory, spatial, or other non-von-Neumann compute targets; Background in hardware design tools such as logic synthesis or place-and-route; Experience building or using cycle-level or performance simulators to guide optimization decisions; Contributions to open-source compiler or kernel infrastructure (e.g., PyTorch, Triton, TVM, MLIR, LLVM); Publishing or presenting compiler or performance work at venues such as MLSys, ASPLOS, or CGO