Front End CAD Engineer

Front End CAD Engineer, Austin, Texas. On-Site, Hybrid work schedule. This is not a remote work opportunity.

Responsibilities

Internal support to project teams for infrastructure, flow development and EDA tools; Collaborate with cross-functional teams to define verification requirements and ensure alignment with overall project goals; Play a crucial role in shaping and optimizing methodologies and EDA workflows, ensuring seamless adoption of industry best practices for crafting efficient System on Chips (SoCs)

Requirements

Several years of in-industry, hands on experience in ASIC IP/ASIC SoC design, RTL, Verilog, and System Verilog, with proficiency in front-end tools including Verilog simulators, debug tools and coverage; Familiarity with synthesis, static timing analysis, and logic equivalence checking; Knowledge of scripting languages such as Perl and Python are required in this role; Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field; Basic understanding of verification methodologies, like UVM, Constrained Random Verification, and formal verification

Benefits

Competitive package; Choice of three medical plan options and a dental plan option; Company credits toward medical and dental premiums; 401(k) Plan with automatic 3% company contribution and matching contributions; Company-paid basic life insurance and basic accidental death and dismemberment coverage; Short-term and long-term disability coverage; Stock Purchase Plan; Minimum of 15 days accrued vacation; Up to 3 personal days per year; 11 annual holidays; 8 hours of volunteer time; 80 hours of sick time annually; Up to 16 weeks of paid maternity leave; 6 weeks of parental or adoption leave at 100% of pay; Financial wellness programs; Educational assistance; Matching gifts; Recognition programs