Intern Verification Engineer

We are looking for a highly motivated Intern/ Working Student who will join our team as an Intern Verification Engineer in Lviv office.

Responsibilities

Develop verification strategy for digital and mixed-signal IC designs.; Verification planning, maintenance, feature extraction, verification tests, coverage and checker development.; Develop reusable verification testbench structures following object-oriented programming principles and methodologies including UVM.; Demonstrates an ability to learn new tool features and procedures.; Attend training courses.; Build up your knowledge and improve your skills using your own research.

Requirements

University student at Electrical Engineering, Computer Engineering, Computer Science or related disciplines.; Preferably university experience in analog/digital design or test engineering.; Knowledge of electrical properties, digital circuits, behavioral modeling and simulation and Unix.; Ability to debug the HW issues.; Ability to prioritize work, set goals and meet deadlines.; Self-motivated and take full responsibility for solutions.; Good written, communication and teamwork skills.; Pre-Intermediate English.

Nice to have

Understanding of HW or FPGA design workflow.; Knowledge of transistor-level integrated circuits and semiconductor physics, PCB design, FPGA, Microcontrollers, Arduino.; Experience with protocols (UART, I2C, SPI, JTAG, etc.).; Programming/scripting (Verilog/VHDL, SystemC/Verilog, TCL, Python, Bash, Perl, C/C++).; Understanding of advanced verification methodologies (e.g. UVM, ABV).; Familiarity with synthesis, P&R, static timing analysis (STA), assertion-based verification and formal verification.; Experience in constrained random verification and metric driven verification.