Senior Engineer, Analog Layout

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

Looking for a 3+ years experienced Engineer with good understanding of analog layout, passion to apply knowledge and build ICs and well versed with layout related flows, to join the 2.6B$ Power Business Unit where in the candidate will get to work on a wide range of exciting products such as PMICs, Linear and Switching DC-DC converters powering the next generation of most sought after phones and hand held devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio.

Responsibilities

Drive and use best practice for floor plan development. Ensure collaboration with designers and layout colleagues to accurately capture requirements, and review floor plan prior to routing to ensure cell dimensions, device placement and pin location are optimal for performance and area.; Use state-of-the-art layout techniques for matching accuracy, parasitic reduction and yield optimization.; Strong use of automation to improve turn around times, including skill programming, TCL, PERL etc.; Routing and verification (DRC, ERC, LVS) of block and circuit level layout.; Organize layout reviews and ensure management is well informed of time scale estimates, progress against project plans and any arising issues.; Demonstrate, and continue to develop, expertise in layout using deep submicron CMOS processes; Demonstrate, and continue to develop, expertise in the required CAD tools (Virtuoso XL / Calibre DRC, LVS & PEX / VCAR / VSR /PVS / R3D).; Mentor junior layout engineers whilst working on more complex tasks.; Follow methodology guidelines to ensure easy portability of IP across designs.; Help resolve issues (CAD / PDK / process) alongside colleagues in corporate engineering.; Suggest improvements to methodology and procedures.; Take proactive approach to driving own development plan, utilizing team members and internal development opportunities.

Requirements

Bachelor’s or Master’s degree in Electrical engineering; 3+ years in Analog Layout design and associated flows.; Must be a natural team player and strive towards fostering a highly creative and productive working environment; Work indepdnently on straightforward tasks, with little direction from manager.; Can exercise judgement within defined procedures to determine best action.; Cross cultural awareness and sensitivity.; Results-oriented and able to deliver on-time under tight schedule .; Ability to work both independently and part of a team.; Flexible to undertake occasional international travel at short notice.; Excellent command of verbal and written English.; Ability to propose innovative solutions.; Concise and precise communication and presentation skills within multisite and multicultural environment.