Senior/Staff/ Sr Staff Engineer, Digital Design

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employees roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.

We are seeking a highly motivated and innovative Senior/Staff/Sr Staff IC Design Engineer (RTL Design) with strong experience in SoC development flows. In this role, you will play a pivotal part in the design and development of advanced integrated circuits that power Renesas MCU products. You will lead complex RTL design efforts, own key IP/subsystem deliverables, mentor junior engineers, and help evolve design methodologies and best practices.

Why Renesas

At Renesas India, you will work on industry-leading MCU platforms, collaborate with global teams, and influence next-generation semiconductor products. This role offers deep technical ownership, growth into architectural leadership, and the opportunity to shape how we design and deliver high-quality silicon.

Responsibilities

Lead RTL design and development of complex IPs and subsystems within MCU SoCs, ensuring compliance with performance, power, and area (PPA) targets; Drive micro-architecture definition and high-level digital design for assigned blocks; Support SoC integration, delivering high-quality subsystem views and documentation to Back-end and Design Verification teams; Own design quality checks, including lint, CDC, and RDC, and actively support functional verification of assigned blocks; Collaborate closely with system architects, verification engineers, physical design teams, and software teams to define specifications and ensure seamless end-to-end integration; Provide technical guidance and mentorship to junior engineers, raising overall team capability and design quality; Contribute to continuous improvement of RTL design methodologies, coding guidelines, and design processes

Requirements

Bachelor’s degree in Electronics & Communication Engineering, Electrical Engineering, Computer Engineering, or related technical field; Minimum of 4 to 8 years of hands-on experience in digital IC/ASIC design, with a strong track record of delivering high-quality silicon; Strong expertise in RTL design using Verilog/VHDL; Solid understanding of digital design principles, timing analysis, clocking, resets, and verification methodologies; Experience using industry-standard EDA tools for synthesis, simulation, and static timing analysis; Strong problem-solving skills with the ability to own blocks end-to-end

Nice to have

Experience owning complex IPs or subsystem designs in large SoCs; Strong background in micro-architecture design and high-level digital design; Hands-on experience with RTL quality tools such as Spyglass (Lint, CDC, RDC); Experience with low-power design techniques and methodologies; Familiarity with SoC-level design and integration; Understanding of synthesis flows and timing constraints; Scripting experience in Shell, Perl, Python or use of AI for design is a strong plus.