Sr. Layout Engineer

We are looking for a new engineer for mask layout design. The successful candidate will play a key role in the mask layout design and development of next-generation LV and MV shielded-gate trench MOSFET technologies. This role involves close collaboration with process integration team and external foundry partners to drive innovation, optimize performance, and accelerate product industrialization.

Mask layout design

T/O procedures

- Schedule adjustment, Provenance tracking
- Define mask specification (Pellicle specification, inspection specification etc.)
- Scribe design, accessary layout such as alignment mark, inspection mark
- Build the related documents including shot map

Responsibilities

Chip layout design for LV/MV shield-gate trench MOSFET based on the design manual/rule (Virtuoso etc.); Verification of mask design rule check (Calibre etc.)

Requirements

More than 5 years of experience in mask layout design for power semiconductor device; Communication skills with product development engineer, process technology engineer.; Intermediate-level proficiency in both written and spoken English and Japanese; More than 10 years of experience in mask layout design for power semiconductor device; English - Can engage in daily conversation (around TOEIC 600 points); Japanese - Can engage in business conversation (above JLPT 2)