Staff Digital Verification Engineer

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

Experience: A minimum of 8+ years in state-of-the-art verification methodologies, specifically in the verification of IP/SoCs. Due to the complexity of our designs .

Complex Design Adaptability: The candidate must quickly adapt and understand complex environments with minimal guidance from our team ,Knowledge of PMIC is an added advantage,

Individual Contributor: We require a self-motivated individual contributor who can manage several tasks, including environment updates, implementing checkers, and adding test cases.

Technical Skills

Communication: The candidate must possess concise, proactive communication skills.

Accountability: Demonstrates ownership of solutions, ensuring their implementation and success.

Requirements

Expertise in System Verilog for verification, preferably using UVM, RAL, and implementing these methodologies.; Proficient in assertion-based verification and knowledge of GLS (Gate-Level Simulation) is a plus.; Skilled in constraint random-driven verification with strong debugging abilities.; Fluent in Verilog RTL coding and ASIC design methodologies .; Bachelor's degree in Computer Science, Computer Engineering, Electronics, or related field (Master's degree preferred); Minimum 8 years of professional experience in digital verification and ASIC design verification