Staff Memory Systems Design Engineer

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.
Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.
Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.

Responsibilities

Role Summary; Key Responsibilities; Own system‑level PCIe Gen5/Gen6 architecture from an NVMe SSD endpoint perspective; Define and review PCIe + NVMe integration across SSD products; PHY + MAC IP review, integration requirements and constraints; SoC/ASIC integration: clocks, resets, power domains, straps, lane mapping, sidebands; PCIe SFR + FW guidelines: flow control, LTSSM observability, power states, error handling; Link & low power transitions: DLRM, L1, L1SS, L0p, ASPM, clock-down, APST Coordination; Bring-up + debug: enumeration, speed negotiation, width detection, stability, AER/error recovery; Customer requirement tuning: latency/power, performance, reliability and consistency; Provide deep expertise in PCIe configuration and extended capability registers, including:; Link, power management, MSI/MSI‑X, AER, BARs, L1SS; Lead platform bring‑up and debug:; Enumeration, link training, speed negotiation, power states, error handling; Act as the technical authority for cross‑team and customer escalations

Requirements

Detailed Responsibilities (End‑to‑End PCIe for NVMe SSD); PHY/MAC IP Review (System Design Perspective); Understand criteria for PHY/MAC/controller IP:; Gen5/Gen6 readiness, equalization capability, margining hooks, lane mapping flexibility; SRNS/SRIS tolerance, clocking modes, power management support; Observability: LTSSM state visibility, error counters, replay/NAK stats, equalization telemetry; Review IP documents:; Reset sequences, compliance features, link speed change support; L1SS behavior, CLKREQ#/REFCLK control expectations; AER robustness, surprise down handling, hot/warm reset behavior; Specify platform-facing requirements:; Retimer/redriver compatibility assumptions (backplane/adaptor/cables); ASIC/SoC Integration Ownership; Integrate PCIe subsystem with:; Clocking: REFCLK handling, clock request gating, clock-down sequences; Resets: PERST# behavior, internal resets, warm/hot resets, FLR support as applicable; Power domains: retention strategies, wake sources, D-state coordination; Sidebands: WAKE#, CLKREQ#, presence detect patterns (platform dependent); Define lane policy:; x4 typical NVMe, lane reversal/polarity, width detection & recovery from degraded width; PCIe SFR / Register + FW Design Guidelines; Define a clean SFR map that FW uses for:; LTSSM control/observability (state, substate, timers, retries); Link speed/width control and status (negotiated vs target); Low-power triggers: ASPM enable/disable, L1SS policy, L0p policy (if implemented)