Korea - Intern - High Speed IO/Datapath Design Engineer

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.

Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.

Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.

Responsibilities

Thorough understanding of High-Speed PHY and Datapath architectures and other clock recovery and schemes.; In-depth knowledge of Timing budgeting and Analysis in custom high-speed designs; Working knowledge of SI/PI Analysis with various models like IBIS/SPF etc; Very analytical in nature and able to work in a multi-disciplinary environment; Creative, out-of-the-box thinker with a high level of personal involvement; Strong theoretical background with a pragmatic approach.; Good verbal and written communication skills and experience working with different geographies.; Good documentation and presentation skills; High level of integrity and commitment to quality and timeliness.

Requirements

We are seeking highly motivated Master’s and Ph.D. candidates with experience in high‑speed interface protocols , including but not limited to: NAND (FLASH) Toggle Mode / ONFI, DDR3/4/5, LPDDR3/4/5, GDDR3/4/5/6, HBM2/3/3E , and other high‑speed interfaces.; Strong understanding of high‑speed PHY and datapath architectures , including clock recovery and related signaling schemes; Proficiency with EDA tools such as Cadence Virtuoso, Synopsys Custom Compiler, HSPICE, Spectre, and FineSim , including statistical simulation methodologies; Experience with mixed‑mode simulation and analog/digital co‑simulation is a plus; Experience in creating EDA models such as Verilog models, Liberty files , etc., is a plus