Principal Engineer, IPD Process Technology

[Hiring Background]

Reneas has set a goal of achieving over USD 20 billion in revenue by 2035 and will continue to expand the possibilities of advanced semiconductor solutions.

Building on this vision, our division is focusing on Intelligent Power Devices (IPD), where the market continues to grow and is taking on the challenge of further expanding our product portfolio.

We are now looking for an experienced leader in the IPD field who can define and drive our specific process roadmap for the IPD product line to enable the optimal process for the development team to provide the best in business products.

Our team values a culture in which members respect and elevate each other's expertise while growing together.

We look forward to applications from candidates who can leverage their past experiences and skills to make a major impact to our division.

[Role Responsibilities]

・Own end-to-end delivery of wafer process development, ensuring robust, scalable, and reliable process release that meets quality, cost, and schedule targets.

・Define the product groups process roadmap. Assessing the present capability and identitying key advancements that will advance the technology for the various IPD product lines

・Includes specification defination that balance design difficulty with market IPD requirements (process tailored for IPD products that will benefit product and design flexibility).

・Understand the mid to long-term wafer process roadmap and contribute to formulating the technology strategy.

・As a technical leader in wafer process development, drive the development in collaboration with the process development team to ensure the reliable release of the processes that meet all requirements.

・Understand reliability and safety standards required for automotive applications (AEC-Q100/012, functional safety ISO 26262, etc.) and reflect them appropriately in the wafer process specification.

・Manage development schedule, cost, risk, and commit to achieving group targets.

・Support wafer process evaluation, analyzing root causes of unexpected results or failures and driving them through to resolution.

・Lead risk identification and mitigation strategies, proactively addressing technical and program risks to ensure predictable execution.

・Mentor and develop less-experienced team members, contributing to raising the overall technical capability of the organization.

[WANT]

- ・Experience and knowledge of CMOS process

- ・Experience and knowledge of TCAD

- ・Experience and knowledge of EMC/ESD

- ・Knowledge of package technology

- ・Knowledge of semiconductor physics

- ・Knowledge of thermal design

Requirements

・8–10+ years of experience in IPD or Power MOS process/device development; ・Experience as a development leader for process/device development, leading multiple developments; ・Extensive knowledge of Power MOS (structure and characteristics) & preferrably FETs used in IPD applications; ・Extensive knowledge of Power MOS driving methods used in IPDs; ・Extensive knowledge of Fault cases and loading for automotive applications; ・Extensive knowledge and experience for rlationship between reliability requiremnt & process/device design; ・Deternination of target specification such as EAS, IAS, TSOA,… & problem solving ability