Senior Analog Engineering Manager

We are seeking a Senior Analog Engineering Manager to lead the development of DDR5 and next-generation DDR6 PHY solutions for advanced SoCs. This role requires deep technical expertise in high-speed memory interfaces, combined with strong people leadership and program ownership.

The successful candidate will manage a team responsible for end-to-end delivery of high-performance, low-power DDR PHYs, from architecture through silicon bring-up, while shaping the roadmap for DDR6-class signaling and architecture

Technical Leadership (DDR5 / DDR6)

People & Organization Leadership

- Build, lead, and mentor a team of analog and mixed-signal designers focused on high-speed memory interfaces.
- Set technical direction, performance expectations, and development plans for senior and principal engineers.
- Drive hiring, onboarding, and team scaling aligned with DDR5 production and DDR6 development needs.
- Foster a culture of technical rigor, ownership, and execution excellence.

Program & Cross-Functional Execution

- Own DDR5/DDR6 PHY execution balancing schedule, quality, and risk
- Partner closely with: Digital PHY and controller teams SoC integration and system architecture, Package, PCB, SI/PI, and validation teams, Product, program management, and customers
- Interface with foundries, IP vendors, and standards bodies as needed to ensure successful delivery and future readiness.

Methodology, Quality & Roadmap

- Establish robust design and signoff methodologies for next-generation high-speed PHYs.
- Drive continuous improvement in simulation accuracy, mixed-signal verification, and silicon debug efficiency.
- Lead long-term DDR5 sustainment and DDR6 technology roadmap planning, including architectural trade-offs and scaling strategies.
- Anticipate challenges from data-rate scaling, power efficiency, and advanced process technologies

Responsibilities

Own and guide the architecture, design, and implementation of DDR5 PHYs and contribute to DDR6-ready architectures.; Provide technical oversight for critical analog and mixed-signal blocks, including:; High-speed TX/RX datapaths; Advanced equalization, termination, and training circuits; DLL/PLL-based clocking solutions for multi-GHz operation; Voltage, reference generation, and power-aware IO design; Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive DDR5/DDR6 data rates.; Ensure compliance with JEDEC DDR5 specifications and alignment with evolving DDR6 standards and industry direction.; Lead post-silicon bring-up, characterization, debug, and yield improvement, including lab and customer-system correlation.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering (PhD preferred).; 12+ years of experience in analog/mixed-signal IC design with deep focus on high-speed memory interfaces.; 5+ years of people-management and technical leadership experience.; Proven hands-on delivery of DDR5 PHYs or late-stage DDR4 designs transitioning to DDR5; Strong expertise in: High-speed IO design and signal integrity, PLL/DLL and low-jitter clocking architectures,Mixed-signal verification and silicon validation, Advanced CMOS process considerations for IOs; High technical credibility with the ability to dive deep when needed; Strong execution mindset with disciplined risk management; Effective mentor and team builder; Strategic thinker with a roadmap-driven approach to DDR evolution; Comfortable balancing hands-on engagement with organizational leadership

Nice to have

Direct involvement in DDR6 architectural studies or early-stage development.; Experience at advanced nodes (7nm, 5nm, and below).; Background in multi-generation memory PHYs or scalable PHY platforms.; Ability to lead teams delivering multiple concurrent tape-outs.; Strong written and verbal communication skills across technical and executive audiences.