Senior Engineer, Packaging Engineering (FIB)

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.

Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.

Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.

We are seeking an experienced Device Physical Failure Analysis (PFA) Engineer with mandatory hands-on SEM and FIB expertise to support advanced semiconductor chip and package development. This role is part of the Chip Package Integration (CPI) Failure Analysis function and plays a key role in improving device reliability and influencing package and product design. The position interfaces closely with wafer fabrication (NAND and ASIC), package and product design teams, electrical and physical characterization, assembly R&D, and other process engineering groups.

Responsibilities

Develop and maintain package recipe and process baselines based on FA findings.; Collaborate with fab process, package design, assembly R&D, and characterization teams.; Evaluate package reliability and robustness in response to fab process changes.; Lead package evaluation and qualification for NAND and ASIC technologies.; Support chip structure optimization through detailed FA results and recommendations.; Perform device-level physical failure analysis (PFA) using SEM and FIB techniques (mandatory).; Conduct FIB cross-sectioning, delayering, and defect localization for root-cause analysis.; Utilize SEM imaging to analyze device structures, interfaces, and failure mechanisms.; Identify and resolve structural and packaging-related reliability issues.; Provide FA insights to influence package and product design decisions.

Requirements

Bachelor’s degree or above in Materials Science, Electrical Engineering, Mechanical Engineering, Physics, or related disciplines.; Strong understanding of device structures, packaging architectures, and failure mechanisms.; More than 3 years hands-on SEM and FIB experience (MUST).; Solid experience in physical failure analysis (PFA) of semiconductor devices.; Good English communication skills, both written and spoken.; Ability to work effectively in cross-functional, global teams.

Nice to have

Background in wafer fab processes and device design.; Experience with NAND and/or ASIC technologies.; Familiarity with electrical and physical characterization methods.; Knowledge of assembly processes and advanced semiconductor packaging.; Experience supporting fab or package process change qualification.