Senior Staff ASIC Design Engineer

Axiado is building the future of AI powered digital infrastructure. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management. Our technology protects the world’s most critical infrastructure—from data centers to next generation cloud and AI platforms—by securing systems at the foundation levels of hardware, independent of host CPUs and operating systems.

Founded in 2019 and now over 150 employees are strong, Axiado has evolved into a recognized leader in the convergence of AI, security, and silicon innovation. We partner with and are actively engaged in commercial programs with multiple Tier 1 industry leaders, validating both our technology and our long-term market trajectory. Axiado has also won numerous industry awards for our ground-breaking products and technological innovations, including being named one of Fast Company’s 2025 Top 10 Most Innovative Companies in Security, winning the 2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliance’s 2025 “Start-Up to Watch” award.

At Axiado, developing breakthrough technology takes more than great engineering—it takes a team of exceptional people who collaborate boldly, challenge assumptions, and take pride in building what comes next. We value curiosity, execution, respect, and a shared desire to make a meaningful impact on the security and reliability of the digital world.

If you’re driven to innovate, energized by hard problems, and excited to help define the future of secure AI infrastructure, we invite you to apply and join us on this journey.

Responsibilities

Help develop the design and implementation/ integration of SoCs.; Micro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks; Support prototyping, test program development, chip validation, and chip life until production maturity.; Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.

Requirements

12+ years of experience in RTL logic design, verification, synthesis, and timing optimization,; Proficient in writing clear, implementable micro-architecture specifications,; Expertise in writing efficient RTL code in Verilog and SoC integration; Good understanding of assertions, coverage analysis, RTL synthesis, and timing closure,; Should have worked on interface protocols like PCIe, USB, Ethernet, DDR/LPDDR4/5, I2C/I3C, eSPI, SPI, etc.; Experience in design bring up and debug on FPGA based emulation platforms like HAPS, Veloce.; Fluency with scripting languages (e.g., Perl, Python),; Must have gone through at least one complete tape-out cycle.; Preferred: Silicon bring-up and debug experience; Experience in working with repository management tools like Bitbucket/ Jenkins and bug tracking tools like JIRA.