Senior Staff Engineer, CAD & Methodology

Renesas is a global semiconductor leader shaping the backbone of next‑generation automotive, industrial, cloud, and IoT innovation. With over $9.3 billion in annual revenue (2024) and a world‑class team of 22,700+ employees, Renesas operates at scale while retaining the agility to drive category‑defining breakthroughs. The company’s footprint spans more than 30 countries, enabling deep customer proximity and a uniquely global innovative engine. As Japan’s semiconductor powerhouse and a top global player in microcontrollers, analog, and power technologies, Renesas delivers real‑world impact across EVs, smart factories, renewable energy infrastructure, and edge intelligence. For ambitious problem‑solvers who want to work on meaningful, systems‑level challenges with huge industry leverage, Renesas offers the scale, stability, and strategic clarity of a market leader—paired with the transformative momentum of a company reinventing how the world computes, connects, and electrifies.

Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.

We are seeking a highly motivated CAD & Methodology Engineer to drive the development, deployment, and support of scalable design automation infrastructure for Backend Physical Design teams. The role focuses on enabling efficient, repeatable, and high-quality RTL-to-GDSII implementation and signoff by maintaining robust reference flows, developing automation solutions, and driving methodology standardization across projects.

The ideal candidate will work closely with Physical Design, Timing, Signoff, EDA vendors, IT infrastructure teams, and Foundry partners to ensure seamless tool deployment, optimized design methodologies, and predictable project execution through tapeout.

Preferred Skills

Join us to drive design automation, methodology innovation, and successful tapeouts across cutting-edge semiconductor products.

Responsibilities

Develop, maintain, and release reference flows for Synthesis, STA, Place & Route, and Signoff.; Build automation to improve productivity, including setup generation, QoR checks, report parsing, ECO automation, and deliverable packaging.; Define and enforce methodology standards, flow validation, and QoR compliance checks.; Qualify and deploy EDA tools, PDKs, libraries, and signoff runsets across compute environments.; Provide technical support and root-cause analysis for flow, tool, and infrastructure issues through tapeout.; Collaborate with Physical Design teams, IT, EDA vendors, and Foundry partners to drive flow improvements and issue resolution.

Requirements

10+ years of experience in Physical Design CAD, Design Methodology, or Backend Design Automation.; Bachelor's or Master's degree in Electronics, Electrical Engineering.; Strong understanding of RTL-to-GDSII implementation and signoff methodologies.; Hands-on experience with industry-standard EDA tools from Synopsys, Cadence, and/or Siemens.; Proficiency in Tcl, Python, Shell, or Perl scripting.; Experience developing CAD automation and methodology solutions for backend design teams.

Nice to have

Experience with advanced technology nodes (7nm and below).; Knowledge of PDK, library, and runset enablement.; Familiarity with compute farms, Linux environments, Git, and CI/CD frameworks.; Strong problem-solving and cross-functional collaboration skills.