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Data publikacji: 03.09.2026
Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.
Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.
-Understanding the expected functionality of designs.
-Designing and developing verification environment
-Improve the verification architecture and flow
-Running RTL and gate-level simulations/regression.
-Code/functional coverage development, analysis and closure.
-Bachelor degree or master degree in CS/ME.
-Minimum of 8 years’ experience.
-Candidate should be familiar with as System Verilog, UVM verification.
-Have Verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
-Independent and self-managing.
Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.
-Understanding the expected functionality of designs.
-Designing and developing verification environment
-Improve the verification architecture and flow
-Running RTL and gate-level simulations/regression.
-Code/functional coverage development, analysis and closure.
-Bachelor degree or master degree in CS/ME.
-Minimum of 8 years’ experience.
-Candidate should be familiar with as System Verilog, UVM verification.
-Have Verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
-Independent and self-managing.
Requirements
Familiar with UVM source code or key UVM mechanism; Familiar with industry standard verification tools and flow.; Familiar with basic computer architecture; Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.; Scripting and automation skills (python) is a plus.; Familiar with C/C++/Java or any object orientation program language, knowledge of software design pattern is a plus; Has experience of setup over 100K lines verification environment; Knowledge of DDR protocol is a plus.; Knowledge of Mixed signal verification is a plusJak aplikować
Aplikuj online: https://www.jobs.pl/oferta/100086835/aplikuj
JOBS.pl · https://www.jobs.pl/sr-staff-digital-verfication-engineer-oferta-100086835



















