(Sr.) Staff Package Design Engineer - MIS substrate/FC expose die (Experienced in Power or Gan is requried)

Job Summary

- Design and develop package and interconnect methods for Renesas’s packaging needs in the areas of Power SiP/modules, wafer level, flip-chip, multi-chip module and power device packaging, GaN related PKG is a plus.
- Package technologies qualification for consumer & industrial power as well as automotive power applications.

Responsibilities

Benchmark, select and qualify suitable materials, processes and assembly subcontractors (OSAT) or contract manufacturers (CM).; Work with OSAT/CM to develop, run DOE to optimize processes, establish process spec & monitor and resolve process issues early in the production to ensure only parts with superior quality shipped to customer.; Work with Product groups and Reliability team, qualify new packages and processes within required time frame & further address internal and external customer complains working with peers of Marketing, Product groups, Quality and Operations organization to satisfy growth in businesses.; Ensure smooth transition into production & implement ramp up monitor.; Participate in packaging roadmap development & focus on execution, develop and maintain technical expertise on advances and innovations in power SiP/modules, wafer level packaging, flip chip interconnects and panel level package.; Establish & maintain package design rules.

Requirements

Doctorate/Masters / Bachelor’s degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering.; >10 years of relevant experience in package development emphasizing power SiP/module, wafer level & flip-chip packaging.; Strong understanding of power SiP/modules, wafer level/flip-chip packaging methods, assembly process knowledge, qualification methods, SPC and statistical analysis software.; Strong interpersonal and communication skills.; Strong analytical and presentation skills.; Knowledge of wire-bonding & multi-chip module technologies is a plus.