Staff Compiler Design Engineer

We are building an MLIR-based compiler and inference stack for custom AI silicon used in telecommunications baseband processing. The compiler takes ML models from StableHLO through orchestration, tiling, memory planning, and code generation onto a multi-core processor architecture with custom accelerators. We already have a working proof point. Real workloads are running on custom silicon at competitive perf-per-watt, and we are building the general-purpose compiler stack around it. This is a small team building something real, not a research project. We are hiring a Principal Compiler Engineer to lead the technical direction of the compiler stack while remaining hands-on in the code. You will make the hard architectural calls, own the pieces of the compiler that determine whether it succeeds, and mentor a growing team of senior compiler engineers. We believe the best architecture comes from the people implementing the system, not from a separate role. This is a hands-on technical leadership role. You will architect, code, review, debug, and profile. If you are looking for a role where you design without shipping, this is not it. You will work directly with hardware architects, runtime developers, and AI researchers, and you will shape both the compiler and how the team builds it. The role requires both breadth, reasoning across the full compiler stack, and depth, going deep on whatever subsystem needs it most at a given moment. We expect this person to move fluidly between architecture, implementation, debugging, and performance analysis.

Responsibilities

Own the technical direction of the compiler stack across model import, lowering, scheduling, memory planning, and code generation; Design and implement the hardest compiler subsystems, the ones that determine whether the compiler achieves its performance and correctness goals; Define MLIR dialect hierarchy, lowering strategy, and pass pipelines in collaboration with the team; Lead hardware-software co-design discussions, partnering with hardware architects to influence instruction set, memory hierarchy, and synchronization mechanisms; Set the technical standards for correctness, determinism, testing, and performance; Mentor Staff and Senior compiler engineers, and shape the technical growth of the team; Represent the compiler team in cross-org technical discussions and roadmap planning

Requirements

Deep experience designing and building production compilers, including significant hands-on ownership of major subsystems; Strong C++ and compiler infrastructure expertise; Hands-on experience with MLIR, LLVM, or another production compiler framework at scale; Track record of shipping compiler work that others build on; Strong understanding of computer architecture and how compilers exploit hardware capabilities; Ability to lead complex technical programs across compiler and hardware teams; Experience mentoring senior engineers and shaping team-level technical decisions

Nice to have

AI accelerator, NPU, DSP, GPU, or VLIW compiler development; Custom MLIR dialects and hardware-specific IRs; Static scheduling and software-managed memory; DMA engines and multi-level memory hierarchies; Quantization, fixed-point, mixed precision, or complex arithmetic; Bare-metal or embedded inference environments; Runtime, firmware, or device-driver integration; Hardware-software co-design for new silicon; StableHLO, XLA, JAX, PyTorch, TensorFlow, or ONNX

Benefits

Competitive compensation package; annual bonus opportunity (Short-Term Variable Compensation Plan/SIP); choice of three medical plan options and a dental plan option; company credits toward medical and dental premiums; 401(k) Plan with automatic 3% company contribution and match up to 4%; company-paid basic life insurance and basic accidental death and dismemberment coverage; short-term and long-term disability coverage; option to participate in Ericsson’s Stock Purchase Plan; minimum 15 days accrued vacation, up to 3 personal days per year, 11 annual holidays, 8 hours volunteer time, and 80 hours sick time annually; up to 16 weeks paid maternity leave and 6 weeks parental or adoption leave at 100% pay; financial wellness programs, educational assistance, matching gifts, and recognition programs